The present invention relates to a semiconductor integrated circuit device and to a technique for manufacturing the same; and, more particularly, the invention relates to a technique suitably applied to the manufacture of a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
A DRAM in recent years employs what is called a stacked capacitor structure in which a capacitive element for storing information is stacked on a memory cell section MISFET to make up for reduction in the storage charge amount of the capacitive element for information storage resulting from miniaturization of the memory cells. DRAMs employing the stacked capacitor structure are broadly divided into a DRAM having a capacitor-under-bitline (CUB) structure in which a capacitive element for information storage is arranged under a bit line (disclosed in, for example, Japanese Unexamined Patent Application Nos. Hei 7 (1995)-192723 and Hei 8 (1996)-204144) and DRAM having a capacitor-over-bitline (COB) structure in which a capacitive element for information storage is disposed over a bitline (disclosed in, for example, Japanese Unexamined Patent Application No. Hei 7 (1995)-122654, U.S. Pat. No. 5,976,929, and Japanese Unexamined Patent Application No. Hei 7(1995)-106437).
In the two kinds of stacked capacitor structures, the COB structure in which a capacitive element for information storage is disposed over a bit line is more suitable for making the memory cell finer for the following reason. In the case of increasing the, storage charge amount of a fine capacitive element for information storage, the structure has to be made three-dimensional to increase the surface area. In the CUB structure in which a bitline is disposed over a capacitive element for information storage, the aspect ratio of a contact hole for connecting a bitline and a memory cell section MISFET becomes extremely high, and it becomes difficult to open the contact hole.
In a recent large-capacity DRAM of 64 Mbits or 256 Mbits, at the time of forming a contact hole for connecting a bit line or a capacitive element for information storage and a substrate in a space between the gate electrodes of a fine memory cell selection MISFET, a self align contact (SAC) technique (disclosed in, for example, Japanese Unexamined Patent Application No. Hei 9(1996)-252098) or a polymetal gate structure (Japanese Unexamined Patent Application No. Hei 7 (1995) -94716) have been employed. In the self align contact technique, the top part and side walls of a gate electrode are covered with a silicon nitride film, and a contact hole is opened in the space between the gate electrodes in a self aligning manner by using an etching rate difference between a silicon oxide film and the silicon nitride film. In the polymetal gate structure, in order to promote a reduction in the resistance of the gate electrode, the gate electrode is mainly made of a high refractory metal material, such as W (tungsten).
The inventors of the present invention have examined the possibility of reduction in bit line capacity as a measure to increase the refresh time interval in the development of a 256-Mbit DRAM and a 1-Gbit DRAM.
Components of the bit line capacity involve a neighboring bit line, a substrate, a storage electrode, a word line, and a plate electrode. In the case of the COB structure in which the capacitive element for information storage is disposed over the bit line, the component for the word line is a main one. In order to reduce the bit line capacity, a highest priority is given to the reduction in the capacity for a word line.
As described above, in a conventional manufacturing process employing the self align contact (SAC) technique, the top part and side walls of a gate electrode are covered with a silicon nitride film having a high etching selectivity to the silicon oxide film. However, the dielectric constant of the silicon nitride is about twice as large as that of the silicon oxide film. When the top part and side walls of the gate electrode are covered with the silicon nitride film, the capacity for a word line of the bit line increases.
An object of the invention is to provide a technique capable of reducing a bit line capacity in a DRAM having fine memory cells.
The above and other objects and novel features of the invention will become apparent from the description in the specification and from the accompanying drawings.
Representative aspects of the invention disclosed in this application will be briefly described as follows.
(1) A semiconductor integrated circuit device of the invention has: a MISFET formed on a semiconductor substrate; contact holes formed on source and drain regions of the MISFET; conductors formed in the contact holes and electrically connected to the source and drain regions; and a first insulating film formed around the conductor, the first insulating film being formed so as to surround the conductor on a bottom part of the contact hole, and at least a part of the first insulating film is removed and the first insulating film is not formed so as to surround the conductor in an upper part of the contact hole.
(2) A semiconductor integrated circuit device of the invention has: a MISFET formed on a semiconductor substrate; contact holes formed on source and drain regions of the MISFET; conductors formed in the contact holes and electrically connected to the source and drain regions; a first side wall insulating film formed so as to surround the conductor; and a second side wall insulating film formed so as to surround the first side wall insulating film, wherein the height of the first side wall insulating film is partially or entirely lower than that of the second side wall insulating film.
(3) A semiconductor integrated circuit device of the invention has: first and second word lines formed on a semiconductor substrate; first and second insulating films formed on the first and second word lines, respectively; a contact hole formed between the first and second word lines; a conductor formed in the contact hole; third and fourth insulating films constructing side walls of the contact hole are formed between the first and second word lines; and a fifth insulting film is formed around the conductor; wherein the level of the fifth insulating film is partially or entirely lower than an upper end portion of each of the third and fourth insulating films.
(4) A process for manufacturing a semiconductor integrated circuit device, having the steps of:
(a) forming a first conductive film on a semiconductor substrate and then forming a first insulating film on the first conductive film;
(b) forming first and second word lines and first and second cap insulating films covering the top portion of each of the first and second word lines by etching the first conductive film and the first insulating film;
(c) forming a first MISFET using a part of the first word line as a gate electrode and a second MISFET using a part of the second word line as a gate electrode;
(d) forming a second insulating film on the semiconductor substrate including a space between the first and second word lines and forming a mask pattern having a slit-shaped opening on the second insulating film;
(e) etching the second insulating film by using the mask pattern having the slit-shaped opening and using the first and second cap insulating films as a mask to thereby form a first opening on one of the source and drain regions of each of the first and second MISFETs and a second opening on the other one of the source and drain regions;
(f) forming a second conductive film in each of the first and second openings; and
(g) forming a bit line electrically connected to one of the source and drain regions via the first opening and forming a capacitive element electrically connected to the other one of the source and drain regions via the second opening.
(5) A process for manufacturing a semiconductor integrated circuit device, having the steps of:
(a) forming a first conductive film on a semiconductor substrate and then forming a first insulating film on the first conductive film;
(b) forming first and second lines and first and second cap insulating films covering the top portion of the first and second lines by etching the first conductive film and the first insulating film;
(c) forming a second insulating film on the semiconductor substrate including a space between the first and second lines and forming a first film having an opening on the second insulating film;
(d) etching the second insulating film by using the first film as a mask and using the first and second cap insulating films as an etching stopper to thereby form an opening in the second insulating film;
(e) forming a side wall insulating film in the opening;
(f) removing a part of the side wall insulating film; and
(g) forming a plug in the opening in which the side wall insulating film is formed.
(6) A process for manufacturing a semiconductor integrated circuit device, having the steps of:
(a) forming a first conductive film on a semiconductor substrate and then forming a first insulating film on the first conductive film;
(b) forming a second insulating film on the first insulating film and then forming a photoresist film on the second insulating film;
(c) etching the first and second insulating films by using the photoresist film as a mask;
(d) forming first and second lines by etching the first conductive film by using the first insulating film as a mask;
(e) forming a third insulating film on a main surface of the semiconductor substrate including a space between the first and second lines and forming a first film on the third insulating film; and
(f) etching the second insulating film by a method in which the etching rate on the first film and the first insulating film is lower than the etching rate on the second insulating film, thereby forming an opening between the first and second lines.